1. Field
Apparatuses and methods consistent with exemplary embodiments relate to a semiconductor device, and more particularly to a method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device and a designing system for arrangement of the TSVs in the stacked semiconductor device.
2. Description of the Related Art
As electronic devices have tended toward miniaturization with a light weight, even semiconductor devices included in the electronic devices are fabricated in a small size with a light weight. Recently, studies and research on a semiconductor device having vertically stacked semiconductor chips, that is, a three dimensional (3D) integrated circuit have been carried out to overcome limitation in a semiconductor integration process and improve a degree of integration of the semiconductor device. In general, the semiconductor chips in the 3D integrated circuit may be electrically connected to one another by using the TSVs.